1. Field of the Invention
The present invention relates to a timing generator for generating a timing signal of a predetermined period, a testing device testing an electronic device, and a skew adjusting method adjusting a skew between interleaved signals in a timing generator using an interleaving method.
2. Description of Related Art
Conventionally, there is known a circuit that generates a set signal and a reset signal of a desired phase and inputs the signals to a set/reset latch to generate a desired pattern. Such a circuit is used in a timing generator that generates a timing signal for a device such as a semiconductor testing device, and generates a timing signal of a desired pattern.
Such a timing generator includes a plurality of set/reset latches to generate a plurality of timing signals at the same time, in order to test a plurality of devices under test and a plurality of pins of the device under test at the same time. Moreover, it is necessary to divide a set signal of a desired phase into a plurality of signals and a reset signal of a desired phase into a plurality of signals corresponding to the plurality of set/reset latches.
FIG. 8 is a view showing a conventional timing generator 400. As described above, the timing generator 400 includes a plurality of set/reset latches 410, a set circuit 420, and a reset circuit 430. Since the set circuit 420 and the reset circuit 430 have the same configuration, it will be described about a configuration of the set circuit 420.
The set circuit 420 includes a variable delay circuit for phase control 440 for controlling a phase of a set signal in accordance with a desired phase and a plurality of variable delay circuits for skew adjustment 450 for adjusting a skew between the divided set signals in order to supply the signals to the plurality of set/reset latches 410. For example, when generating four timing signals, the four set/reset latches 410 and the four variable delay circuits for skew adjustment 450 are required, and thus the set signal is divided into four signals.
Moreover, the set circuit 420 generates a set signal based on a reference clock of a semiconductor testing device. However, since the frequency of reference clock is constant, the set circuit 420 interleaves the reference clock to generate the set signal when generating a timing signal of a higher frequency. As shown in FIG. 8, when performing two-way interleaving, the set circuit 420 has two variable delay circuits for phase control 440. Thus, the set circuit 420 generates the first set signal and the second set signal that are controlled respectively to have a desired phase, in which the phases are different from each other by half cycle.
Moreover, in this case, the eight variable delay circuits for skew adjustment 450 are required to respectively divide the first set signal and the second set signal into four signals. Then, OR circuits 460 respectively generate a logical sum of the first set signal and the second set signal to supply the logical sum to the set/reset latch 410 as the set signal. In this case, the variable delay circuits for skew adjustment 450 adjust a skew between the first set signal and the second set signal in addition to a skew between the timing signals.
However, in a case where the conventional timing generator 400 generates the set signal and the reset signal by the interleaving method as described above, a plurality of variable delay circuits for skew adjustment 450 is required. For this reason, there has been a problem that the power consumption of the timing generator 400 increases. Particularly, since it is required that a variable delay circuit for adjusting a skew generate a highly precise delay, there are required a circuit and a control for reducing a variation in a delay amount by the change of working factor, thereby increasing the power consumption.